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silego technology, inc. rev 1.00 000-005nth1011-100 revised april 5, 2017 SLG5NTH1011V a 22 v, 50 m , 3 a reverse blocking integrated power switch with vin lockout select and mosfet current monitor output block diagram and a 20 v / 3 a typical application circuit general description the SLG5NTH1011V is a high-performance, self-powered 50 m ? nmos power switch with ba ck-to-back reverse-current blocking designed for all 4.5 to 22 v power rails up to 3a. using a proprietary mosfet design, the SLG5NTH1011V achieves a stable 50 m ? rds on across a wide input/supply voltage range. using silego?s proprietary cufet? technology, the SLG5NTH1011V package also exhibits a low thermal resis- tance for high-current operation. designed to operate over a -40 c to 85 c range, the SLG5NTH1011V is available in a low thermal resistance, rohs-compliant, 1.6 x 3.0 mm stqfn package. features ? wide operating supply voltage: 4.5 v to 22 v ? maximum continuous switch current: 3 a ? back-to-back fet reverse current blocking, when off ? internal nfet power limiting ? high-performance mosfet switch low rds on : 50 m ? at v in = 22 v low ? rds on / ? v in : <0.05 m ? /v low ? rds on / ? t: <0.06 m ? /c ? 4-level, pin-programmable v in overvoltage lockout ? capacitor-adjustable inrush current control ? two stage current limit protection: resistor-adjustable active current limit internal short-circuit current limit ? open drain fault signaling ? mosfet current analog output monitor: 10 a/a ? pb-free / halogen-free / rohs compliant packaging pin configuration applications ? power-rail switching ? multifunction printers ? large-format copiers ? telecommunications equipment ? high-performance computing 4.5 v and 22 v point-of-load power distribution ? motor drives on 1 fault cap gnd sel0 2 3 15 16 vin 4 vout sel1 13 14 rset 18 iout vin vin 5 6 vin 7 vout 12 vout vout 10 11 17 vin vout 89 18-pin stqfn 1.6 x 3.0 mm, 0.40mm pitch (top view) SLG5NTH1011V on 3 v fs - connect to system adc connect to system gpi charge pump c slew 10 nf r pu2 100 k linear ramp control state machine (cl/sc detection and over temperature protection) cmos input vin ovlo 24v r set 30.1 k c 1 47 f gnd off c 2 1 to 22 f c 3 0.1 f v logic r pu1 10 k v logic sel0 sel1 vout cap rset vin iout fault on 20 v in 3a r iout. 84.5 k c load 22 f c iout. 18 nf c in = c 1 + c 2 + c 3
000-005nth1011-100 page 2 of 20 SLG5NTH1011V pin description ordering information pin # pin name type pin description 1 on input a low-to-high transition on this pin initiates the operation of the SLG5NTH1011V?s state machine. on is an asserted high, level-sensitive cmos input with v il < 0.3 v and v ih > 0.85 v. as the on pin input circuit does not have an internal pull-down resistor, connect this pin to a general-purpose output (gpo) of a microcontroller, an applic ation processor, or a system contro ller ? do not allo w this pin to be open-circuited. 2 sel0 input as level-sensitive, cmos inputs with v il < 0.3 v and v ih > 1.65 v, the sel0 (lsb) and the sel1 (msb) pins select one of four v in overvoltage lockout thresholds. please see the applications section for additional informa tion and the electrical characteristics table for the v in overvoltage thresholds. a logic low on either pin is achieved by connecting the pin of interest to gnd; a logic high on either pin is achieved by connecting a 10 k ? external resistor from the pin in quest ion to the system?s local logic supply. 3gnd gnd pin 3 is the main ground connection for the SLG5NTH1011V?s internal charge pump, its gate drive and current-limit circuits as well as its internal state machine. therefore, use a short, stout connection from pin 3 to the system?s analog or power plane. 4-8 vin mosfet vin supplies the power for the operation of the SLG5NTH1011V, its internal control circuitry, and the drain terminal of the back-to-back, reverse-blocking nfet power switch. with 5 pins fused toget her at vin, connect a 47 f (or larger) low-esr capacitor from this pin to ground. capacitors used at vin should be rated at 50 v or higher. 9-13 vout mosfet drain terminal of n-channel mosfet (5 pins fused for vout). connect a 22 f (or larger) low-esr capacitor from this pin to ground. ca pacitors used at vout should be rated at 50 v or higher. 14 sel1 input please see sel0 pin description above 15 fault output an open drain output, fault is asserted within tfault low when a v in overvoltage, a current-limit, or an ov er-temperature condition is detected. fault is deasserted within tfault high when the fault condition is removed. connect an 100 k external resistor from the fault pin to local system logic supply. 16 cap output a low-esr, stable dielectric, ceramic surfac e-mount capacitor connected from cap pin to gnd sets the v out slew rate and overall turn-on time of the SLG5NTH1011V. for best performance, the range for c slew values are 10 nf c slew 20 nf ? please see typical characteristics for additional information. ca pacitors used at the cap pin should be rated at 10 v or higher. please consult applications section on how to select c slew based on v out slew rate and loading conditions. 17 iout output iout is the SLG5NTH1011V?s power mosfet load current monitor output. as an analog output current, this signal when applied to a ground-reference resistor generates a voltage proportional to the current through the n-channel mosfet. the i out transfer characteristic is typically 10 a/a with a voltage compliance range of 0.5 v v iout 4 v. optimal i out linearity is exhibited for 0.5 a i ds 3 a. in addition, it is recommended to bypass the iout pin to gnd with a 0.18 nf capacitor. 18 rset input a 1%-tolerance, metal-film resistor between 30 k and 95 k sets the SLG5NTH1011V?s active current limit. a 95 k resistor sets the SLG5NTH1011V?s active current limit to 1 a and a 30 k resistor sets the acti ve current limit to 3 a. part number type production flow SLG5NTH1011V stqfn 18l fc industrial, -40 c to 85 c SLG5NTH1011Vtr stqfn 18l fc (tape and reel) industrial, -40 c to 85 c
000-005nth1011-100 page 3 of 20 SLG5NTH1011V absolute maximum ratings parameter description conditions min. typ. max. unit v in to gnd power switch input voltage to gnd continuous -0.3 -- 30 v maximum pulsed v in , pulse width <0.1s -- -- 32 v v out to gnd power switch output voltage to gnd -0.3 -- vin v on, sel[1,0], cap, rset, iout, and fault to gnd on, sel[1,0], cap, rset, iout, and fault pin voltages to gnd -0.3 -- 7 v t s storage temperature -65 -- 150 c esd hbm esd protection human body model 2000 -- -- v esd cdm esd protection charged device model 500 -- -- v msl moisture sensitivity level 1 ja thermal resistance 1.6 x 3.0 mm 18l stqfn; de- termined with the device mount- ed onto a 1 in 2 , 1 oz. copper pad of fr-4 material -- 40 -- c/w t j,max maximum junction temperature -- 150 -- c mosfet ids cont continuous current from vin to vout t j < 150c -- -- 4 a mosfet ids peak peak current from vin to vout maximum pulsed switch current, pulse width < 1 ms, 1% duty cy- cle -- -- 5 a note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a s tress rating only and functional operation of the device at these or any other conditions above thos e indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condition s for extended periods may affect reliability. electrical characteristics 4.5 v v in 22 v; c in = 47 f, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c parameter description conditions min. typ. max. unit v in operating input voltage 4.5 -- 22 v v in(ovlo) v in overvoltage lockout threshold v in ; sel[1,0] = [0,0] 5.6 6 6.3 v v in ; sel[1,0] = [0,1] 10.2 10.8 11.4 v v in ; sel[1,0] = [1,0] 13.5 14.4 15.2 v v in ; sel[1,0] = [1,1] 22.6 24 25.2 v v in(ovlohyst) v in overvoltage lockout hysteresis -- 2 -- % v in(uvlo) v in undervoltage lockout threshold v in 33.23.4v i q quiescent supply current on = high; i ds = 0 a -- 0.5 0.6 ma i shdn off mode supply current on = low; i ds = 0 a -- 1 3 a rds on on resistance t a = 25c; i ds = 0.1 a -- 50 52 m ? t a = 85c; i ds = 0.1 a -- 65 68 m ?
000-005nth1011-100 page 4 of 20 SLG5NTH1011V mosfet ids current from vin to vout continuous -- -- 3 a i reverse mosfet reverse-leakage current v in = 0 v ; v out = 22 v ; on = 0 v -- -- 3 a i limit active current limit, i acl v out > 0.5 v; r set = 30.1 k ? 33.23.4a short-circuit current limit, i scl v out < 0.5 v -- 0.5 -- a t acl active current limit response time r set = 51.6 k ? -- 120 -- s i out mosfet current analog monitor out- put i load = 1 a 9.3 10 10.7 a i load = 3 a 28.53031.5 a t iout i out response time to change in main mosfet current c iout = 180 pf; step load 0 to 2.4 a; 0% to 90% i out -- 45 -- s c load output load capacitance c load connected from vout to gnd -- 22 -- f t on_delay on delay time 50% on to 10% v out ; v in = 4.5 v; c slew = 10 nf; r load = 100 ? , c load = 10 f -- 0.3 0.5 ms 50% on to 10% v out ; v in = 22 v; c slew = 10 nf; r load = 100 ? , c load = 10f -- 0.7 1.2 ms t to t a l _ o n total turn-on time 50% on to 90% v out set by external c slew ms 50% on to 90% v out ; v in = 4.5 v; c slew = 10 nf; r load = 100 ? , c load = 10 f -- 1.5 2.1 ms 50% on to 90% v out ; v in = 22 v; c slew = 10 nf; r load = 100 ? , c load = 10 f -- 6.5 8 ms v out(sr) v out slew rate 50% on to 90% v out set by external c slew v/ms 10% to 90% v out ; v in = 4.5 to 22 v; c slew = 10 nf; r load = 100 ? , c load = 10 f 2.7 3.2 3.9 v/ms t off_delay off delay time 50% on to v out ; r load = 100 ? , no c load -- 15 -- s t fall v out fall time 90% v out to 10% v out ; on = high-to-low; v in = 4.5 v to 22 v; r load = 100 ? , no c load 10.4 12.7 14.3 s tfault low fault assertion time abnormal step load current event to fault ; i acl = 1 a; v in = 22 v; r set = 95 k ? ; switch in 20 ? load -- 80 -- s tfault high fault de-assertion time delay to fault after fault condition is removed; i acl = 1 a; v in = 22 v; r set = 95 k ? ; switch out 20 ? load -- 180 -- s fault vol fault output low voltage i fault = 1 ma -- 0.2 -- v on_v ih on pin input high voltage 0.9 -- 5 v on_v il on pin input low voltage -0.3 0 0.3 v sel[1,0]_v ih sel[1,0] pins input high voltage 1.65 -- 4.5 v electrical characteristics (continued) 4.5 v v in 22 v; c in = 47 f, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c parameter description conditions min. typ. max. unit
000-005nth1011-100 page 5 of 20 SLG5NTH1011V t total_on , t on_delay and slew rate measurement timing details sel[1,0]_v il sel[1,0] pins input low voltage -0.3 -- 0.3 v i on(leakage) on pin leakage current 1v on 5v or on = gnd -- -- 1 a therm on thermal protection shutdown thresh- old -- 125 -- c therm off thermal protection restart threshold -- 100 -- c notes: 1. refer to typical timing parameter vs. c slew performance charts for additi onal information when available. electrical characteristics (continued) 4.5 v v in 22 v; c in = 47 f, t a = -40c to 85c, unless otherwise noted. typical values are at t a = 25c parameter description conditions min. typ. max. unit 90% v out 50% on t on_delay v out(sr) (v/ms) on* v out t to t a l _ o n 10% v out 50% on 10% v out t off_delay t fall 90% v out * rise and fall times of the on signal are 100 ns
000-005nth1011-100 page 6 of 20 SLG5NTH1011V typical performance characteristics rds on vs. temperature and v in i acl vs. temperature and r set
000-005nth1011-100 page 7 of 20 SLG5NTH1011V i acl vs. r set i out vs. mosfet ids and v in
000-005nth1011-100 page 8 of 20 SLG5NTH1011V i out vs. temperature and mosfet ids v out slew rate vs. temperature, v in , and c slew
000-005nth1011-100 page 9 of 20 SLG5NTH1011V t total_on vs. c slew , v in , and temperature
000-005nth1011-100 page 10 of 20 SLG5NTH1011V timing diagram - basic operation including active current limit protection v in on time low high 3.5 v tfault high v out i ds 90% 10% t on_delay active current limit operation fault 0.25 v high i scl i acl i scl i acl on tfault low nominal steady state operation resumes acl threshold triggered abnormal step load current event t rise
000-005nth1011-100 page 11 of 20 SLG5NTH1011V timing diagram - active current limit & thermal protection operation v out i ds 90% 10% t on_delay active current limit operation thermal protection operation i scl i acl i scl i acl tfault high fault v in on time low high 3.5 v nominal steady state operation resumes tfault low die temp > therm on abnormal step load current event t rise t to ta l _ o n die temp < therm off
000-005nth1011-100 page 12 of 20 SLG5NTH1011V timing diagram - basic operation including active current + internal fet soa protection v in on time low high 3.5 v tfault high v out i ds 90% 10% 0.2s t on_delay active current limit operation fault 0.25 v high i scl i acl i scl i acl on tfault low acl threshold triggered nominal steady state operation resumes once overload condition is removed automatic restart after 0.2s ?cool off? delay and normal operation resumes if overload condition is removed fet soa threshold triggered and fet is turned off acl threshold triggered abnormal step load current event soa threshold t rise decreasing r load drops v out soa protection
000-005nth1011-100 page 13 of 20 SLG5NTH1011V applications information hfet1 safe operating area explained silego?s hfet1 integrated power controllers incorporate a number of internal protection featur es that prevents them from damaging themselves or any other circuit or subcircuit downstr eam of them. one particular protection feature is their safe operation area (soa) protection. soa pr otection is automatically activated under overpower and, in some cases, under overcurrent conditions. overpower soa is activated if package po wer dissipation exceeds an internal 5w threshold longer than 2.5 ms. hfet1 devices will quickly switch off (open circuit) u pon overpower detection and automatically resume (close) nominal operation once overpower condition no longer exists. one possible way to have an overpower condition trigger soa pr otection is when hfet1 products are enabled into heavy output resistive loads and/or into large load capacitors. it is u nder these conditions to follow carefully the ?safe start-up loading? guidance in the applications section of the datasheet. during an overcurrent condition, hfet1 devices will try to limit the out put current to the level set by the external r set resistor. limiting the output current, however, causes an increased voltage drop across the fet?s channel because the fet?s rds on increased as well. since the fet?s rds on is larger, package power dissipation also increases. if the resultant increase in package pow er dissipation is higher/equal than 5 w for longer than 2.5 ms, internal soa protection will be triggered a nd the fet will open circuit (switch off). every time soa protection is triggered, a ll hfet1 devices will automatically attempt to resume nominal operation after 160 ms. safe start-up condition SLG5NTH1011V has built-in protection to prevent over-heating during start-up into a heavy load. overloading the vout pin with a capacitor and a resistor may result in non-monotonic v out ramping. in general, under light loading on v out , v out ramping can be controlled with c slew value. the following equation serves as a guide: where t rise = total rise time from 10% v out to 90% v out v in = input voltage c slew = capacitor value for cap pin when capacitor and resistor loading on v out during start up, the following tables will ensure v out ramping is monotonic without triggering internal protection: safe start-up loading for v in = 22 v (monotonic ramp) slew rate (v/ms) c slew (nf) 3 c load ( f) r load ( ) 0.5 66.7 500 80 1.0 33.3 250 80 1.5 22.2 160 80 2.0 16.7 120 80 2.5 13.3 100 80 c slew = t rise v in x 5 a x 20 3
000-005nth1011-100 page 14 of 20 SLG5NTH1011V note 3: select the closest-value tolerance capacitor. setting the SLG5NTH1011V?s active current limit note 4: active current limit accuracy is 15% over voltage range and over temperature range. setting the SLG5NTH1011V?s input overvoltage lockout threshold as shown in the table below, sel[1,0] selects the v in overvoltage threshold at which the SLG5NTH1011V?s internal state machine will turn off (open circuit) the power mosfet if v in exceeds the selected threshold. for example, sel[1,1] would be the most appropriate setting for app lications where the steady-state v in can extend up to 20v without causing any damage to the SLG5NTH1011V since the ic is 29-v tolerant. with an activated SLG5NTH1011V (on=high) and at any time v in crosses the programmed v in overvoltage threshold, the state machine opens the power switch and asserts the fault pin within tfault low . in applications with a deactivat ed or inactive SLG5NTH1011V (v in > v in(ovlo) and on=low) and if the applied v in is higher than the programmed v in(ovlo) threshold, the SLG5NTH1011V?s state machine will keep the power switch open circuited if the on pin is toggled low-to-high. in these cases, the fault pin will also be asserted within tfault low and will remain asserted until vin resumes nominal, steady-state operation. in all cases, the SLG5NTH1011V?s v in undervoltage lockout threshold is fixed at v in(uvlo) . safe start-up loading for v in = 12 v (monotonic ramp) slew rate (v/ms) c slew (nf) 3 c load ( f) r load ( ) 1 33.3 500 20 2 16.7 250 20 3 11.1 160 20 4 8.3 120 20 5 6.7 100 20 r set (k ? ) active current limit (a) 4 95 1 45 2 30 3 sel1 sel0 v in(ovlo) (typ) 00 6 0 1 10.8 1 0 14.4 11 24
000-005nth1011-100 page 15 of 20 SLG5NTH1011V power dissipation the junction temperature of the slg5nth 1011v depends on different factors such as board layout, ambient temperature, and other environmental factors. the primary c ontributor to the increase in the junction temperature of the SLG5NTH1011V is the power dissipation of its power mosfet. its power dissipation an d the junction temperature in nominal operating mode can be calculated using the following equations: where: pd = power dissipation, in watts (w) rds on = power mosfet on re sistance, in ohms ( ? ) i ds = output current, in amps (a) and where: t j = junction temperature, in celsius degrees (c) ja = package thermal resistance, in celsius degrees per watt (c/w) t a = ambient temperature, in celsius degrees (c) in current-limit mode, the SLG5NTH1011V?s power dissipation can be calculated by taking into account the voltage drop across the power switch (v in -v out ) and the magnitude of the output current in current-limit mode (i acl ): where: pd = power dissipation, in watts (w) v in = input voltage, in volts (v) r load = load resistance, in ohms ( ? ) i acl = output limited current, in amps (a) v out = r load x i acl pd = rds on x i ds 2 t j = pd x ja + t a pd = (v in -v out ) x i acl or pd = (v in ? (r load x i acl )) x i acl
000-005nth1011-100 page 16 of 20 SLG5NTH1011V package top marking system definition 1011v part code pin 1 identifier wwnnn date code + lot code arr assembly + rev. code 1011v - part id field ww - date code field 1 nnn - lot traceabi lity code field 1 a - assembly site code field 2 rr - part revision code field 2 note 1: each character in code field can be alphanumeric a-z and 0-9 note 2: character in code field can be alphabetic a-z
000-005nth1011-100 page 17 of 20 SLG5NTH1011V package drawing and dimensions 18 lead tqfn package 1.6 x 3 mm (fused lead) jedec mo-220, variation wcee
000-005nth1011-100 page 18 of 20 SLG5NTH1011V SLG5NTH1011V 18-pin stqfn pcb landing pattern note: all dimensions s hown in micrometers ( m)
000-005nth1011-100 page 19 of 20 SLG5NTH1011V tape and reel specifications carrier tape drawing and dimensions recommended reflow soldering profile please see ipc/jedec j-std-020: late st revision for reflow profile based on package volume of 2.64 mm 3 (nominal). more information can be found at www.jedec.org. package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 18l 0.4p fc green 18 1.6 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w stqfn 18l 0.4p fc green 1.78 3.18 0.76 4 4 1.5 1.75 3.5 8 refer to eia-481 specification
000-005nth1011-100 page 20 of 20 SLG5NTH1011V revision history date version change 4/5/2017 1.00 production release

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